Tcl, Verilog, System Verilog, Python, AI tools, digital design flow, ASIC Design, Rtl Design, GitHub Copilot

Arm Assembly, Perl, Ethernet, Python, System Verilog, PCIe PHY, Object-Oriented Design, SERDES, Uvm, EDA Verification tools

Java, Unix, CGI, HTML, Perl, Python, Component Testing, Cadence, fabrication process, DRAM operation, semiconductor device physics, advanced packaging, wafer testing, DFII, module testing

Yaml, Perl, Scripting Languages, Python, Tcl, Allegro Package Designer, signoff tools, EDA Tools, 3D-IC system planning, Cadence digital flows

UNIX, Ovm, Linux, Verilog, Python, Perl, Pcie, DDR, systemverilog, low-power verification using CPF UPF, Uvm, CHI, Ace, AMBA, FPGA emulation prototyping platforms, VHDL, AI LLM-based approaches, formal verification methodologies, Axi

Python Scripting, routing, Perl, Tcl, CTS, floorplan placement, Cadence-lnnovus, place and route tools, integrity tool, commercial place route tools, 3DIC designs, Synopsys-lCC2, Physical Design, Timing Closure, 3DIC compiler, Aprisa