C, Perl, Arm, Python, Digital multi core SoC verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation, RISC-V Assembly, RN Real Number Digital top-level modeling

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

power integrity , Perl, Python, Tcl, FinFET process technologies, Ansys RedHawk-SC, Quantus PrimePower, Cadence Voltus, physical-design implementation, Joules, EMIR analysis, StarRC, current and activity models

Excel, Python, Ms Word

Pytorch, Python, Git, Numpy, Version Control Systems, Pandas, prompt engineering, machine learning frameworks, OpenAI’s GPT models, data processing libraries, Hugging Face

Python, PERL, Debugging, Silicon Validation, analog simulation, silicon bring-up, Analog Circuit Design, noise analysis, stability and compensation, CMOS technology, device mismatch and variation, virtuoso