IR EM Analysis, SI PI Analysis, Physical Verification, Floorplanning and Power Planning, Low Power Design UPF CPF, STA and Timing Closure, Physical Design and Signoff, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows

Physical Synthesis, Critical-path SPICE simulation, floorplanning, Timing analysis and closure, ECO implementation, Timing sign-off methodologies, Placement Routing, Physical design sign-off, Timing Constraints, RTL-to-GDSII physical implementation flow, Power optimization and convergence, Full-chip timing closure, PPA optimization

IR EM Analysis, SI PI Analysis, Floorplanning and Power Planning, Physical Verification, Low Power Design UPF CPF, STA and Timing Closure, Tcl Python Scripting, Physical Design and Signoff, Advanced Node Design Methodologies, Clock Architecture and CTS, AI-assisted Design Flows

IR EM Analysis, SI PI Analysis, Physical Verification, Floorplanning and Power Planning, Low Power Design UPF CPF, STA and Timing Closure, Physical Design and Signoff, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows

redhawk , floorplanning, place-and-route, LVS, Cadence Innovus, EDA Tools, EM, Fusion Compiler, IR drop, Physical Design, primetime, Synopsys ICC2, Voltus, Timing Closure, DRC, Clock Tree Synthesis