C, Perl, Arm, Python, Digital multi core SoC verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation, RISC-V Assembly, RN Real Number Digital top-level modeling

Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

Excel, Python, Ms Word