Python, protocol analyzers, signal generators, 1.6T switches, Ethernet traffic generators, BER testers, spectrum analyzers

code coverage , Scsi, DDR, PERL, Pcie, Verilog, Sata, Python, Usb, Nvme, Tcl, LINT, Design Compiler, Digital ASIC Design methodology, cdc, primetime, Rtl Design, Synthesis, DisplayPort, assertions, Formality, Timing Analysis, systemverilog, Axi, AMBA, Eco, HDMI, CXL, AHB, Design Verification CAD tools, NCSim

Clarity, Mentor Xpedition, Q3D, Crosstalk Analysis, electromagnetics, Transmission Line Theory, Ads, Pcb Design, Sentinel-PSI, Hspice, APD, SIP, DDR SerDes, hfss, Package Design, Cadence Allegro

Ansys, Python, multi-port network parameters, SI PI analysis tools, pre-layout SI PI design guidelines, Linux environments, electromagnetic extraction methodologies, Cadence

C, Computer Architecture, Python, coverage analysis, checkers, memory hierarchy, microarchitecture fundamentals, UVM-based verification, debug infrastructure, systemverilog, scoreboards, constrained-random verification, cache architecture, testbenches, cache coherency protocols, assertions, coverage models

power meters , C, Perl, Python, Sampling Oscilloscopes, Network Analyzers, ATE testing