Perl, Python, verification methodologies, low power verification, system level performance analysis, Uvm, systemverilog, RTL development environments, test bench infrastructure, emulation platforms, test plan development, automation scripts

Spi, Uart, Usb, Verilog, I2c, Python, Perl, Can, safety simulators, GLS, vManager, Uvm, Specman, systemverilog, Xcelium, Cadence Tools, AI ML-based DV, VHDL, post-silicon verification, AHB, Formal JG applications, PAGLS

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Verilog, systemverilog, Rtl Design, Verification Manager, Test Bench