Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi