Tcl, Python, Perl, routing, floorplanning, UPF, RTL-to-GDSII execution, Physical Verification, automated design methodologies, LVS closure methodologies, Ir, Placement, CTS, signoff, Sta, low-power design strategies, ECO flows, physical signoff, CPF, Synthesis, Si, EM analysis, DRC

static timing analysis, EDA tools for synthesis, digital design principles, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, RTL quality tools such as Spyglass Lint CDC RDC

Python, Static timing analysis, Unix, Splunk, AI ML, Linux, Lsf, Bitbucket, Jenkins, Git, make, EDA Tools, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, DesignSync, Dft, Design revision control, Power-aware flows

Lsf, Unix, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, Python, GenAI, VLSI CAD, CI CD process, DesignSync, make, reinforcement learning, Design revision control, Dft, Design Verification, EDA Tools, Power-aware flows, Convolutional Networks, Graph Neural Networks

ethernet ip , C, Fpga, Python, Rtos, Linux, ASIC, Communications Protocols, TCP-IP, Firmware Verification, Embedded Systems

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

power system studies , MATLAB, Technical Specifications, Protection and control philosophies, PVSys, PSCAD, Earthing and lightning protection systems, UPS DC systems, Generators, Lighting system layouts, BESS electrical equipment, HOMER, Electrical cables, Control Architecture, PSSE, SCADA system, SKM, Transformers, GIS system, Protection relays, BESS integration, Etap, Electrical Systems

Pcie, Verilog, Ethernet, Prototyping, Python, Scripting, Tcl, UCIe chiplet interconnects, AI tools, cdc, area optimization, Emulation, systemverilog, high-speed IO protocols, Rtl Design, formal verification, RDC, LINT, Timing Closure, silicon bring-up, CXL, micro-architecture, power efficiency