C, Python, LabVIEW, Analog Digital and Mixed signal IPs, DMM, Oscilloscopes, Bench Characterization, signal generators, SMUs

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

Mac, Switch, Pcie, 1G Ethernet, UFS, SV, XUSB, High Speed IO verification, verification tools for simulation and debug, Uvm

Verilog, System Verilog, CPU architecture, Coherent fabric designs, debugging skills, ARM knowledge

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Perl, Vcs, Python, Tcl, Incisive, Verdi, DVE, Questa, Uvm, systemverilog