Git, Visual Studio, Agile Development, Python, Board-level debugging, RapiTest, Hardware software integration, Wind River VxWorks

Tcl, Python, Perl, routing, floorplanning, UPF, RTL-to-GDSII execution, Physical Verification, automated design methodologies, LVS closure methodologies, Ir, Placement, CTS, signoff, Sta, low-power design strategies, ECO flows, physical signoff, CPF, Synthesis, Si, EM analysis, DRC

static timing analysis, EDA tools for synthesis, digital design principles, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, RTL quality tools such as Spyglass Lint CDC RDC

synopsys primetime , Shell Scripting, Perl, Python, Tcl, Tempus, SI OCV AOCV POCV CDC, Setup Hold Analysis, StarRC, Timing Exceptions, Low-Power Timing Methodologies, Timing Convergence Techniques, Timing Signoff

Python Programming, PLAXIS 2D, Leapfrog Geo, Rhino, CAD parametric modelling, Itasca FLAC2D, Numerical Modelling, Grasshopper, Rocscience suite, rock mechanics, geotechnical engineering

Python, Static timing analysis, Unix, Splunk, AI ML, Linux, Lsf, Bitbucket, Jenkins, Git, make, EDA Tools, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, DesignSync, Dft, Design revision control, Power-aware flows

Nosql, Java, Restful Apis, Kubernetes, Python, Sql, AI productivity tools, Go, AI ML technologies

C++, Linux, Bash, Python, Kubernetes, CI/CD