Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

System Verilog, Building test benches from scratch, Data path verification performance tests, Gate level simulation, ASIC verification using UVM, formal verification

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA

C, Perl, Computer Architecture, Ruby, Python, SV-UVM, Uvm

System Verilog, Building test benches from scratch, ASIC verification using UVM

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

Verilog, random stimulus, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog