Tcl, Python, Synthesis, Timing Closure, formal verification, RTL netlist quality check, Chip integration and netlist generation, Constraints creation and validation

Python, Tcl, Function eco creation, Timing budget, Constraints creation and validation, RTL netlist quality check, Chip partitioning, Timing Closure, Synthesis, formal verification, Chip Integration, Floorplan, Netlist generation, Flow automation development