Scripting automation, Advanced FinFET node designs, SoC Physical Design, Calibre, ASIC Design, Cadence PnR STA tools

layout verification , Tcl, DRC fixes, power analysis, place and route implementation, advanced technology nodes, Timing Closure, Cadence Innovus, lower power design, Synopsys ICC2

thermal management , Perl, Python, Tcl, Design for Yield and Manufacturability, Advanced technology nodes, floorplanning, Hierarchical design pinning and budgeting flows, Chip Assembly, Industry-standard EDA tools, Power distribution networks, RTL-to-GDS flow, FSDB SAIFs for power optimization, Place and route techniques, Physical Design Engineering, Timing Analysis, Power and clock distribution, IR and EM analysis

Usb, DDR, Shell, Pcie, Python, Tcl, SoC FPGA integration, chip-level communication protocols, Axi, MIPI, APB, Timing Closure, FPGA architecture synthesis, SoC emulation methodologies, AHB, FPGA utilization

code coverage , Scsi, DDR, PERL, Pcie, Verilog, Sata, Python, Usb, Nvme, Tcl, LINT, Design Compiler, Digital ASIC Design methodology, cdc, primetime, Rtl Design, Synthesis, DisplayPort, assertions, Formality, Timing Analysis, systemverilog, Axi, AMBA, Eco, HDMI, CXL, AHB, Design Verification CAD tools, NCSim

power meters , C, Perl, Python, Sampling Oscilloscopes, Network Analyzers, ATE testing

protocol analyzer , Windows, Test automation, Linux, Python, Traffic analyzer, Oscilloscope, C Language, BER tester, Analog Mixed Signal application, Logic Analyzer, TCL programming