Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

power integrity , Tcl, Python, Perl, Shell, Physical Design signoff, Ansys RedHawk, Cadence Voltus, IR EM analysis

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols