power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

routing, congestion analysis, IR drop, primetime, floorplanning, physical ECO implementation, physical optimization, Cadence Innovus, LVS, Power Planning, Physical Verification, antenna checks, Calibre, Physical Design, StarRC, ERC, Timing Closure, DRC, Placement, sign-off, RTL-to-GDSII, Synopsys ICC2

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Placement and Routing, Timing Closure, Physical Design Implementation

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm