Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

power integrity , Tcl, Python, Perl, Shell, Physical Design signoff, Ansys RedHawk, Cadence Voltus, IR EM analysis

Logic Design, Synopsys, MBIST OCC validation flows, IEEE 1687 IJTAG standards, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, Cadence, DFT for complex ASIC SoC designs, SSN design, Physical design flows, RTL design synthesis

Servicenow, Github, Automated Testing, Microservices, Typescript, Python, Apis, Jira, Git, retrieval systems, LangGraph, multi-agent workflows, A2A, enterprise AI governance, LLM-powered applications, Vertex AI, Anthropic Bedrock, observability, cloud-native applications, event-driven systems, Production Operations, tool-calling architectures, AI agents, MCP, OpenAI