Debug Root Cause Analysis, Verification Planning, Uvm, SoC Verification, systemverilog, Functional Coverage, Assertion-based Verification

assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification

shell scripting, Verilog, Python, Tcl, Sta, SDC constraints, cdc, synchronizers, multi-reset SoC designs, asynchronous FIFOs, systemverilog, reset sequencing, RDC, debugging RTL timing, LINT, synthesis tools

static timing analysis, Automation Frameworks, Verilog, low-power implementation methodologies, design constraints, generative AI tools, functional validation, AI-assisted engineering technologies, systemverilog, Rtl Design, Logic Synthesis, EDA Tools, Timing Closure

Ml, Python, Tcl, Sta, Synthesis, power-state tables, power-gating, Fusion Compiler, Physical Verification, low-power flows, Ai, isolation, Innovus, PnR flows, FM VSI, level-shifter, voltage areas, UPF concepts, electrical checks

Shell, Perl, Makefile, Ruby, Innovus, Fusion compiler, primetime, EDA Tools, Lower node technologies, Toplevel Physical implementation, Processor designs

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification