synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Python, Tcl, OCV, primetime, Low-Power UPF, SI Crosstalk, CRPR, Cadence Tempus, MMMC, Eco, POCV, SDC Constraints, CPF, AOCV, LVF

Linux Scripting, Python, Debugging, triaging, orchestration systems, Vlsi, AI GenAI systems, EDA Tools, agent frameworks

Static Timing Analysis, Architectural Circuit Co-Optimization, primetime, Physical Design, Tempus, Circuit-Level Timing Noise Integrity, Synopsys Fusion Compiler, Cadence Innovus, Clock Distribution Circuit Design, Interconnect Physical Design

Tcl, Python, PERL, LVS, Synthesis, Synopsys, EM Signoff, Formal Equivalence, DRC, Ir, Mentor, Cadence