Git, Visual Studio, Agile Development, Python, Board-level debugging, RapiTest, Hardware software integration, Wind River VxWorks

synopsys primetime , Tcl Scripting, timing closure techniques, Synthesis, ECO methodologies, Physical Design, signal integrity debugging, Extraction, process variation analysis

synopsys primetime , Shell Scripting, Perl, Python, Tcl, Tempus, SI OCV AOCV POCV CDC, Setup Hold Analysis, StarRC, Timing Exceptions, Low-Power Timing Methodologies, Timing Convergence Techniques, Timing Signoff

Perl, Python Scripting, Shell, HBT Compact Modeling, HBT

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

System Verilog, formal verification methodologies, C testcases, scripting for flow integration, Uvm, AI ML-driven EDA tools

data engineering , Cloudformation, Cloud Infrastructure, Sql, ELT, Microservices, Jenkins, Data Pipeline, Terraform, Data Architecture, Data Lake, Data Warehousing, Api, Security Compliance, AWS, Etl, Infrastructure as Code, Dimensional Data Modelling, GitLab CI, GitHub Actions, Observability, Monitoring

Rtos, Device Drivers, Linux kernel, Exception Handling, trusted firmware, Caches, CPU Microarchitecture Knowledge, bring-up and debugging skills, ARM v8 v9 architecture, MMU, hypervisors, interrupts, debug subsystems, Low-level firmware and architecture-specific code