Matlab, Worst case identification, Process technologies, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Simulation on modern CAD tools, Analog Circuit Design, Architectural tradeoff analysis, Schematic generation, Routing tradeoffs, Spectre, Cadence tool set, Signal grounding, Top level simulation, Simplis, device physics, Post layout parasitic extraction, Die area optimization

C, Perl, Python, Tcl, high-speed IO circuits, modelling and simulating high-speed interface interconnects and channels, LVS, RC circuit fundamentals, post-layout extraction tools, Spectre Prime-Sim, Custom Compiler, Hspice, CMOS design, DRC, Virtuoso ADE, Verilog-A

Scripting, C, Verilog, Python, PCB design and layout software, Amplifiers, Signal integrity analysis, Noise reduction techniques, Analog Circuits Design, Transistor level circuit design, EMIR flows, Spice, Primesim, virtuoso, Reliability, Bias circuits

bandgap references , Pspice, Statistics, MOS Diodes, Analog Circuit Design, Transistor layout fabrication process, Monte Carlo analysis, Level Shifter, Schmitt Trigger, Statistical Distributions, LDMOS, ESD protection circuits for CMOS IC, Power FETs, Amplifiers, Current Mirrors, Comparators