C, Perl, Arm, Python, RISC-V Assembly, digital Verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

I2c, Python, PCB back-end process, DFA, Logic Analyzers, LPDDR4 5, Buck and Boost PMIC, Oscilloscopes, PCIe interface Gen5 Gen6, LDO Load Switch devices, Dfm, SMBus, DC-DC converters, ONFI interface, Power Analyzers, I3C, NAND memories, PCIe analyzers

C, Python, LabVIEW, Analog Digital and Mixed signal IPs, DMM, Oscilloscopes, Bench Characterization, signal generators, SMUs

System Verilog, SystemVerilog Assertions, Functional Code Coverage, Bluetooth BLE Technologies, constraint random tests, HDLs like Verilog, SV UVM environments, Formal checks, debugging RTL TB issues using Verdi or similar tools, Functional Verification, SoC Integration

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog