Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Python, Tcl, OCV, primetime, Low-Power UPF, SI Crosstalk, CRPR, Cadence Tempus, MMMC, Eco, POCV, SDC Constraints, CPF, AOCV, LVF

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus

control logic , Processor microarchitecture, CPU datapath expertise, Physical design implementation, ALUs, Execution units, Block-level tape-outs, FPUs, RTL to GDS implementation, Data-paths, High-speed digital logic

Machine Learning, Eda, Automation, Shell, Perl, Python, Tcl, CAD, Ai, RTL-to-GDSII flows, Physical Design, EDA Tools, Silicon Engineering

synopsys tools , Perl, Tcl, SoC integration, high-speed designs, ICC2, Process Improvements, Physical Verification, flow automation, Floor Planning, Calibre, Innovus, Netlist2GDSII implementation, power grid design, Tk