Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Physical design implementation, Synthesis, Signoff implementation tools, PPA optimization, Scripting skills, RTL to GDS implementation

Rcp, Tcl Scripting, automation, Rc, Perl, Primepower, Sta, Constraints Signoff, Physical Design, UPF, Rtl Design, Synthesis, ASIC Design, high speed CPU implementation, low power checks, low power design, DCG, PowerArtist, place and route tool understanding, CPU micro-architecture, timing and power analysis, primetime, DCT, CPF

control logic , Verilog, Sta, Synthesis, PCS link training, IEEE 802.3 Ethernet, state machines, systemverilog, cdc, RDC, Rtl Design