synopsys tools , Perl, Tcl, SoC integration, high-speed designs, ICC2, Process Improvements, Physical Verification, flow automation, Floor Planning, Calibre, Innovus, Netlist2GDSII implementation, power grid design, Tk

routing, static timing analysis, physical design methodologies, place and route tools, floorplanning, Placement

power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Placement and Routing, Timing Closure, Physical Design Implementation

Tcl, PERL, Cadence Innovus, Tk

redhawk , Tcl, Python, Perl, Scripting Languages, Tempus, manufacturing sign-off, multi-clock domain handling, advanced nodes, ASIC SoC physical design, PrimeClouser, Cadence Innovus, Timing Analysis, Physical Verification, EDA Tools, DFT insertion, Calibre, EM IR analysis, primetime, Signal Integrity, low-power design, Voltus, reliability checks, power analysis