C++, Perl, Python, RTL Verilog, Uvm, systemverilog, SVA

Verilog, Scripting Languages, Ethernet, systemverilog, Uvm, low power design, Functional Verification, Testbench Development, Simulation Tools, Debugging Techniques, Timing Analysis

Integration, System Verilog, Test Planning, testbench stimulus agent monitor checker development, ASIC Design, Verification, coverage driven constraint random verification, Uvm, Validation, c based reference model

Networking, Pcie, Test Methodologies, Ethernet, Axi, AMBA

C, C++, Vcs, Debugging, RTL simulation, on-chip bus protocols, Xcelium, Uvm, systemverilog, SoC-level verification, AMBA, Axi, APB, Questa, AHB, functional coverage

Python, Tcl, Innovus, primetime, Fusion Compiler, StarRC, Genus, Tempus