power integrity , Verilog, Debugging, Matlab, system level timing budget, lab instrumentation, PLL for high speed IO interfaces, Cadence custom design tools, Signal Integrity, Tx Rx CDR, timing analysis tool, Data Converters, silicon bring-up, circuit simulator, NanoTime

Verilog, Matlab, Hspice, XA FineSim, Cadence custom design environments, Spectre, Deep submicron CMOS FinFET processes, Device reliability, Esd, Mixed-Signal Analog circuit design, Latch-Up requirements, NanoTime