rc extraction , Perl, Python, Tcl, Cadence EDI, Makefile scripts, Mentor Calibre, Ansys Redhawk, physical verification tools, Clock Power Distribution, Timing Closure, EDA Tools, Synopsys ICV, Synopsys ICC2

Perl, Python, Tcl, Function eco creation, Timing Closure, Synthesis, formal verification, Netlist quality check, STA for hierarchical design, Constraints creation and validation, Flow automation development

rc extraction , Perl, Python, Tcl, VLSI physical design, STA design constraint, Timing Analysis, EM analysis, Make scripting, RTL2GDS, Timing Closure, Floor Planning, IR drop analysis