UNIX, Verilog, Debugging, design quality checks, SoC connectivity concepts, Simulation, RTL integration, Digital Design, Windows environments, systemverilog, RTL Coding, Ms Office Tools, ASIC SoC design methodologies

Firmware Development, FPGA Design, Verilog, Static Timing, ASIC design flow, Synthesis, datapath timing analysis, digital design principles, high-speed data transmission, systemverilog, CMOS digital circuits, Rtl Design, Dft, front-end tools, mixed signal concepts, Verification, clock design

control logic , Verilog, Rtl Design, Synthesis, systemverilog, Error handling, cdc, Sta, Ethernet standards, Digital micro-architecture, PCS functionality, Link monitoring, state machines, Packet processing, RDC, Safety mechanisms

Verilog, System Verilog, Synthesis, VHDL, digital timing analysis, RTL Coding, lint CDC RDC constraint development, RTL micro architectures development, Digital Design

static timing analysis, Synthesis, multi-power-domain design techniques, Simulation, Uvm, FPGA design methodologies, formal verification tools such as Siemens Questa Formal and Synopsys Spyglass

static timing analysis, Perl, Python, LINT, EDA tools for synthesis, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Shell, Tcl, Verilog, Python, Perl, Modelsim, Uvm, LINT, Questa Formal, systemverilog, JasperGold Formal, Cadence VCS, VHDL, Makefiles, QuestaSim, Cadence Xcelium

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation