assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Perl, automation, Python, Tcl, regression management, verification methodologies, debug methodologies, AI-assisted workflows, Uvm, systemverilog, constrained-random verification, assertions, verification metrics, functional coverage

Debugging, Python, Tcl, C, formal verification, Uvm, systemverilog, dpi, ISO 26262, Automotive Networking Technologies, SoC Verification

State-of-the-art tools, Design Verification, Verification expertise