High-Speed ADC Design, Analog IC Design, Mixed-Signal IC Design, Cadence Virtuoso

Matlab, Worst case identification, Process technologies, Monte Carlo analysis, Simulation verification, Block level topology selection, Physical layout management, IC system partitioning, AMs, Simulation on modern CAD tools, Analog Circuit Design, Architectural tradeoff analysis, Schematic generation, Spectre, Routing tradeoffs, Cadence tool set, Signal grounding, Top level simulation, Simplis, device physics, Post layout parasitic extraction, Die area optimization