static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Verilog, System Verilog, Linear Control Theory, power management, High Bandwidth Linear Amplifiers, Cadence ADE, Transistor Reliability, UVI Techniques, Electro-Migration, Mixed signal circuits, behavioral modeling, Very Low Power References, MathWorks MATLAB, Analog Front Ends, High Accuracy Data Converters, VerilogAMS, Power Electronics

Matlab Simulink, RTL Verilog, mixed-signal verification, digital PWM modulators, digital design tools, systemverilog

UVM (Universal Verification Methodology), System Verilog Assertions (SVA), C, Verilog, Debugging, systemverilog, Regression management, Assertion-based verification, JasperGold Formal, Xcelium simulator, Verdi Debugger, Checkers, Verification automation tools and scripts, Bus functional models, Functional coverage-driven verification, NAND flash memory protocols, Scoreboards, Memory design verification, Monitors, Formal verification tools

C, Shell, Verilog, Python, Systemc, Test Planning, Tcl, power-aware verification using UPF, systemverilog, constrained-random verification, transaction-level modeling, formal verification, assertions, UVM-based testbench development, NoC bus and interconnect verification