Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Static Timing Analysis, Architectural Circuit Co-Optimization, primetime, Physical Design, Tempus, Circuit-Level Timing Noise Integrity, Synopsys Fusion Compiler, Cadence Innovus, Clock Distribution Circuit Design, Interconnect Physical Design